A method for testing a memory circuit by using a built-in self test (BIST) circuit incorporated into a semiconductor integrated circuit along with the memory circuit has been proposed. For example, the BIST circuit replaces, with refresh, an access more than the maximum address of each of a plurality of memory circuits with different address bit widths. Then, the BIST circuit performs the reading and writing of data from and to the plurality of memory circuits in parallel by prohibiting a comparison between read data and an expected value at the time of refresh. Japanese Laid-open Patent Publication No. 2000-163993 is an example of related art.